82443GX Datasheet, PDF (121/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Testability
Testability
6
This section provides information about the testability features of the 82443GX.
6.1
Test Mode Activation
The primary test mode is enabled via the TESTIN# pin. To enable a test mode, the TESTIN# input
pin is asserted low and a 5-bit binary pattern is presented on the PCI PREQ[4:0]# input pins. The
following tables show the PREQ[4:0]# signal encoding for test modes enabled via TESTIN# pin.
Table 6-1. Test Modes
PREQ[2:0]#
000
001
110
111
Test Mode Enabled
NAND Chain A
NAND Chain B
Normal Operation
Normal Operation
Table 6-2. Output Modes
PREQ[4:3]#
00
11
Test Mode Enabled
Tristate all Outputs
Enable all Outputs (default)
Normal Operation is the normal operating mode of 82443GX. The 82443GX enters this mode
during power up (as long as the TESTIN# pin is tied off to high) and stays in this mode for the
duration of its operation.
No primary test mode is accessible during normal operation. The Tristate All Outputs test mode is
used to tristate all bi-directional and output-only pins. This can be used as a debugging technique
on the motherboard. During this test mode, all pullups and pulldowns are also disabled.
Figure 6-1 shows the sequence required to enable a primary test mode. Note that the TESTIN#
input pin acts as a latch enable, and the PREQ[4:0]# pins act as latch inputs. The test mode is
decoded from the output of the latch.
82443GX Host Bridge Datasheet
6-1