82443GX Datasheet, PDF (13/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Architectural Overview
DRAM Interface
The 82443GX integrates a DRAM controller that supports a 64-bit main memory interface. The
DRAM controller supports the following features:
• DRAM type: Synchronous DRAM (SDRAM) controller optimized for dual/quad-bank
SDRAM organization on a row by row basis
• Memory Size: 16 MB to 2 GB with eight memory rows
• Addressing Type: Asymmetrical addressing
• Memory Modules supported: Single and double-sided 3.3V DIMMs
• DRAM device technology: 16 Mbit, 64 Mbit, 128 Mbit, and 256 Mbit¹
• DRAM Speed: 100 MHz synchronous memory (SDRAM).
The Intel^® 440GX AGPset also provides DIMM plug-and-play support via Serial Presence Detect
(SPD) mechanism using the SMBus interface. The 82443GX provides optional data integrity
features including ECC in the memory array. During reads from DRAM, the 82443GX provides
error checking and correction of the data. The 82443GX supports multiple-bit error detection and
single-bit error correction when ECC mode is enabled and single/multi-bit error detection when
correction is disabled. During writes to the DRAM, the 82443GX generates ECC for the data on a
QWord basis. Partial QWord writes require a read-modify-write cycle when ECC is enabled.
AGP Interface
The 82443GX AGP implementation is compatible with the following:
• The Accelerated Graphics Port Specification, Rev 1.0
• Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96)
The 82443GX supports only a synchronous AGP interface coupling to the 82443GX core
frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using
133 MHz AGP compliant devices).
PCI Interface
The 82443GX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to
five external PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM
interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec
for streaming writes.
System Clocking
The 82443GX operates the host interface, SDRAM, and core at 100 MHz only; PCI at
33 MHz; and AGP at 66/133 MHz.
I/O APIC
I/O APIC is used to support dual processors as well as enhanced interrupt processing in the single
processor environment. The 82443GX supports an external status output signal that can be used to
control synchronization of interrupts in configurations that use PIIX4E with stand-alone I/O APIC
component.
1. Proper operation of the 82443GX AGPset with 256-Mbit SDRAM devices has not yet been verified. Intel’s current plans are to validate this feature
in the second half of 1998 when 256-Mbit SDRAM devices are available.
82443GX Host Bridge Datasheet
1-3