82443GX Datasheet, PDF (76/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.4.12
3.4.13
3.4.14
3.4.15
SUBUSN—Subordinate Bus Number Register (Device 1)
Offset:
Default:
Access:
Size:
1Ah
00h
Read /Write
8 bits
This register identifies the subordinate bus (if any) that resides at the level below AGP.This number
is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.
Bit
7:0 Bus Number. Programmable.
Descriptions
SMLT—Secondary Master Latency Timer Register
(Device 1)
Address Offset:
Default Value:
Access:
Size:
1Bh
00h
Read/Write
8 bits
This register control the bus tenure of the 82443GX on AGP the same way the Device 0 MLT
controls the access to the PCI bus.
Bit
Description
7:3 Secondary MLT Counter Value. The default is 0s (i.e,. SMLT disabled)
2:0 Reserved.
IOBASE—I/O Base Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Ch
F0h
Read/Write
8 bits
This register control the CPU to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
Bit
Description
7:4 I/O Address Base. Corresponds to A[15:12] of the I/O address. Default = Fh
3:0 Reserved.
IOLIMIT—I/O Limit Address Register (Device 1)
Address Offset:
Default Value:
Access:
Size:
1Dh
00h
Read/Write
8 bits
This register controls the CPU to AGP I/O access routing based on the following formula:
IO_BASE=< address =<IO_LIMIT
3-52
82443GX Host Bridge Datasheet