82443GX Datasheet, PDF (47/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
Row Boundary Address
These 8 bit values represent the upper address limits of the eight rows (i.e., this row minus previous
row = row size). Unpopulated rows have a value equal to the previous row (row size = 0). DRB7
reflects the maximum amount of DRAM in the system. The top of memory is determined by the
value written into DRB7.
Note: The 82443GX supports a maximum of 2 GB of DRAM.
As an example of a general purpose configuration where eight physical rows are configured for
either single-sided or double-sided DIMMs, the memory array would be configured like the one
shown in Figure 3-2. In this configuration, the 82443GX drives eight CS# signals directly to the
DIMM rows. If single-sided DIMMs are populated, the even CS# signals are used and the odd
CS#s are not connected. If double-sided DIMMs are used, all four CS# signals are used per DIMM.
Figure 3-2. SDRAM DIMMs and Corresponding DRB Registers
CSA7#/CSB7#
CSA6#/CSB6#
CSA5#/CSB5#
CSA4#/CSB4#
CSA3#/CSB3#
CSA2#/CSB2#
CSA1#/CSB1#
CSA0#/CSB0#
DIMM3 – Back
DIMM3 – Front
DIMM2 – Back
DIMM2 – Front
DIMM1 – Back
DIMM1 – Front
DIMM0 – Back
DIMM0 – Front
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
The following 2 examples describe how the DRB Registers are programmed for cases of single-
sided and double-sided DIMMs on a motherboard.
Example #1 Single-sided DIMMs
Assume a total of 32 MB of DRAM are required using single-sided 2 MB x 64 DIMMs. In this
configuration, two DIMMs are required.
DRB0 = 02h
DRB1 = 02h
DRB2 = 04h
DRB3 = 04h
DRB4 = 04h
DRB5 = 04h
DRB6 = 04h
DRB7 = 04h
populated (1 DIMM, 16 Mbyte this row)
empty row
populated (1 DIMM, 16 Mbyte this row)
empty row
empty row
empty row
empty row
empty row
82443GX Host Bridge Datasheet
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