82443GX Datasheet, PDF (102/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
Note: Any ECC errors received during initialization should be ignored.
After a single-bit correctable ECC error has occurred, it is reported either via hardware mechanism
or via software mechanism (periodic polling of the ERRSTS register). After a single bit error has
occurred, the 82443GX then initiates a write to the location where the error occurred with the
corrected data. This feature is known as hardware scrubbing and eliminates the need for software
scrubbing routines. Note that information in the ERRSTS register can be used later to point to a
faulty DRAM DIMM if the single-bit errors continually occur during access to that DIMM.
Multi-bit uncorrectable errors are fatal system errors and will cause the 82443GX to assert the
SERR# signal, if bit 1 of the ERRCMD register is set to 1. When an uncorrectable error is detected,
the 82443GX will latch the row # where the error occurred Multi-bit First Row Error (MBFRE) bit
in the ERRSTS register. This information can be used later to point to a faulty DRAM DIMM.
Note: When ECC is enabled, the whole DRAM array MUST be first initialized by doing writes before the
DRAM read operations can be performed. This will establish the correlation between 64-bit data
and associated 8-bit ECC code which does not exist after power-on.
4.6.1.5
Optimum ECC Coverage
Note that the 82443GX requirement is only that the memory array is 72 bits (64 bit memory data
bus plus 8 ECC check bits) wide to select ECC or EC protection. The 82443GX does not assume
any specific configuration or ordering of memory bits.
4.6.2
DRAM ECC Error Signaling Mechanism
When ECC is enabled and ERRCMD is used to set SERR# functionality, ECC errors are signaled
to the system via the SERR# pin. The 82443GX can be programmed to signal SERR# on
uncorrectable errors, correctable errors, or both. The type of error condition is latched until cleared
by software (regardless of SERR# signaling).
When a single-bit error is detected, the offending DRAM row ID is latched in the Single-bit First
Row Error (SBFRE) field in the ERRSTS register and the SEF (Single-bit Error Flag) bit is set to 1.
The latched row value is held until software explicitly clears the error status flag (SEF bit). When a
multiple-bit (uncorrectable) error is detected, the offending DRAM row ID is latched in the Multi-
bit First Row Error (MBFRE) field in the ERRSTS register and the MEF (Multi-bit Error Flag) is
set to 1. The latched row value is held until software explicitly clears the error status flag (MEF
bit).
4.6.3
CPU Bus Integrity
The Intel^® 440GX AGPset does not support the Pentium Pro processor bus integrity mechanisms.
It does not provide support for data protection via ECC, and address/request signal protection via
parity, nor does it support bus protocol error checking or reporting.
4.6.4
PCI Bus Integrity
The 82443GX implements Parity generation on the PAR pin as defined by the PCI Rev. 2.1
Specification for both Primary and Secondary PCI bus. The 82443GX does not contain the PERR#
pin, however the 82443GX will check and report data parity errors on either the Primary or
Secondary PCI buses. Data and address parity errors are reported on SERR#.
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82443GX Host Bridge Datasheet