82443GX Datasheet, PDF (66/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
Bit
Description
CSA5#, CSB5#. This bit enables 100 MHz buffers for CSA5#, CSB5#.
12
0 = Reserved
1 = 100 MHz
CSA4#, CSB4#. This bit enables 100 MHz buffers for CSA4#, CSB4#.
11
0 = Reserved
1 = 100 MHz
CSA3#, CSB3#. This bit enables 100 MHz buffers for CSA3#, CSB3#.
10
0 = Reserved
1 = 100 MHz
CSA2#, CSB2#. This bit enables 100 MHz buffers for CSA2#, CSB2#.
9
0 = Reserved
1 = 100 MHz
CSA1#, CSB1#. This bit enables 100 MHz buffers for CSA1#, CSB1#.
8
0 = Reserved
1 = 100 MHz
CSA0#, CSB0#. This bit enables 100 MHz buffers for CSA0#, CSB0#.
7
0 =Reserved
1 = 100 MHz
DQMA5. This bit enables 100 MHz buffers for DQMA5.
6
0 = Reserved
1 = 100 MHz
DQMA1. This bit enables 100 MHz buffers for DQMA1.
5
0 = Reserved
1 = 100 MHz
DQMB5. This bit enables 100 MHz buffers for DQMB5.
4
0 = Reserved
1 = 100 MHz
DQMB1. This bit enables 100 MHz buffers for DQMB1.
3
0 = Reserved
1 = 100 MHz
DQMA[7:6,4:2,0]. This bit enables 100 MHz buffers for DQMA[7:6], DQMA[4:2], and DQMA[0].
2
0 = Reserved
1 = 100 MHz
GCKE. This bit enables 100 MHz buffers for GCKE.
1
0 = Reserved
1 = 100 MHz
FENA. This bit enables 100 MHz buffers for FENA.
0
0 = Reserved
1 = 100 MHz
3.3.37
BSPAD—BIOS Scratch Pad Register (Device 0)
Address Offset: D0–D7h
3-42
82443GX Host Bridge Datasheet