82443GX Datasheet, PDF (22/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-6. AGP Interface Signals (Sheet 3 of 3)
Name
GGNT#
GAD[31:0]
GC/BE[3:0]#
GPAR
Type
O
AGP
I/O
AGP
I/O
AGP
I/O
AGP
Description
Graphics Grant: Same meaning as PCI but additional information is provided on
ST[2:0]. The additional information indicates that the selected master is the recipient
of previously requested read data (high or normal priority), it is to provide write data
(high or normal priority), for a previously queued write command or has been given
permission to start a bus transaction (AGP or PCI).
Graphics Address/Data: Same as PCI.
Graphics Command/Byte Enables: Slightly different meaning. Provides command
information (different commands than PCI) when requests are being queued when
using PIPE#. Provide valid byte information during AGP write transactions and are
not used during the return of read data.
Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI
transactions as defined by the PCI specification.
NOTE:
1. AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by
the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue
addresses the master is not allowed to queue addresses using the SBA bus. For example, during
configuration time, if the master indicates that it can use either mechanism, the configuration software will
indicate which mechanism the master will use. Once this choice has been made, the master will continue to
use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This
change of modes is not a dynamic mechanism but rather a static decision when the device is first being
configured after reset.
2. PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For
transactions on the AGP interface carried using PCI protocol these signals completely preserve PCI
semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6.
3. The LOCK# signal is not supported on the AGP interface (even for PCI operations).
4. PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI
transactions on the AGP Interface.
2.6
Clocks, Reset, and Miscellaneous
Table 2-7. Clocks, Reset, and Miscellaneous (Sheet 1 of 2)
Name
HCLKIN
PCLKIN
DCLKO
DCLKWR
PCIRST#
GCLKIN
Type
I
CMOS
I
CMOS
O
CMOS
I
CMOS
I
CMOS
I
CMOS
Description
Host Clock In: This pin receives a buffered host clock. This clock is used by all of the
82443GX logic that is in the Host clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
PCI Clock In: This is a buffered PCI clock reference that is synchronously derived by
an external clock synthesizer component from the host clock. This clock is used by all
of the 82443GX logic that is in the PCI clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
SDRAM Clock Out: 100 MHz SDRAM clock reference. It feeds an external buffer
clock device that produces multiple copies for the DIMMs.
SDRAM Write Clock: Feedback reference from the external SDRAM clock buffer.
PCI Reset: When asserted, this signal will reset the 82443GX logic. All PCI output
and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1
specifications.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal.
2-8
82443GX Host Bridge Datasheet