82443GX Datasheet, PDF (104/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Functional Description
Low-Power Modes Supported by the 82443GX
The 82443GX supports a variety of system-wide low power modes using the following functions:
• Hardware interface with PIIX4E is used to indicate:
— Suspend mode entry.
— Resume from suspend.
— Whether to reset “resume logic” during resume from Suspend to Disk (STD).
— Whether to automatically switch from suspend to normal refresh
• Automatic transition from normal to suspend refresh.
• Optional automatic transition from suspend to normal refresh.
• Optional CPU reset during resume from Power On Suspend (POS).
• Self Refresh for SDRAMs is the support suspend refresh type.
• I/O pins isolation to significantly reduce power consumption while in POS and STR modes.
Based on the above functions, the 82443GX distinguishes the following system-wide low power
modes:
• STR and POS suspend entry and exit are generally handled in the same manner. The following
exceptions are related to POS:
— POS resume sequence may or may not include CPU reset. STR, with PCIRST# active
always includes CPU reset.
— POS resume sequence requires hardware transition from suspend to normal refresh. STR,
with PCIRST# active requires software initiated transition.
• STD resume is handled the same as power on sequence, including complete reset of 82443GX
state.
Clock Control Functions Supported by 82443GX
• Internal clock gating: this function allows the 82443GX to gate the clock to the majority of its
logic while there is no pending events to handle.
• The Primary PCI bus includes the support of the CLKRUN#, which enables the PIIX4E to
dynamically disable the primary PCICLK and for the 82443GX and PCI peripheral to re-
enable the clock when it is needed to perform a transaction.
• When an AGP port is not available on the system, a strapping option allows the 82443GX to
permanently disable all clocks associated with AGP logic.
SMRAM Functions
The 82443GX provides the normal SMRAM range mapping, in the areas below 1MB, as well as
extended SMRAM ranges that are mapped in cacheable ranges above 1MB. In addition, the
82443GX provides the normal control mechanism to initialize, close for data accesses and lock the
SMRAM range.
Summary of ACPI Functions
The 82443GX provides an optional decoding of pm2_control register in IO port 22h. This IO port
can be used to disable the 82443GX arbiters for PCI and AGP initiated cycles.
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82443GX Host Bridge Datasheet