82443GX Datasheet, PDF (18/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Signal Description
Table 2-3. DRAM Interface Signals (Sheet 2 of 2)
Name
Type
Description
MAA[14:0]
MAB[12:11]#
MAB[14,13,10]
MAB[9:0]#
WEA#
WEB#
MD[63:0]
MECC[7:0]
O
CMOS
O
CMOS
I/O
CMOS
I/O
CMOS
Memory Address(SDRAM): MAA[14:0] and MAB[14,13,12#,11#,10,9#:0#] are
used to provide the multiplexed row and column address to DRAM. There are two
sets of MA signals which drive a max. of 2 DIMMs each. MAB[12:11,9:0]# are
inverted copies of MAA[12:11,9:0]. MAA[14,13,10] and MAB[14,13,10] are
identical copies. Each MAA/MAB[14:0] line has a programmable buffer strength to
optimize for different signal loading conditions.
Write Enable Signa: WE# is asserted during writes to DRAM. The WE# lines
have a programmable buffer strength to optimize for different signal loading
conditions.
Memory Data: These signals are used to interface to the DRAM data bus.
Memory ECC Data: These signals carry Memory ECC data during access to
DRAM.
2.3
PCI Interface (Primary)
Table 2-4. Primary PCI Interface Signals (Sheet 1 of 2)
Name
AD[31:0]
DEVSEL#
FRAME#
IRDY#
Type
I/O
PCI
I/O
PCI
I/O
PCI
I/O
PCI
Description
PCI Address/Data: These signals are connected to the PCI address/data bus.
Address is driven by the 82443GX with FRAME# assertion, data is driven or received
in the following clocks. When the 82443GX acts as a target on the PCI Bus, the
AD[31:0] signals are inputs and contain the address during the first clock of FRAME#
assertion and input data (writes) or output data (reads) on subsequent clocks.
Device Select: Device select, when asserted, indicates that a PCI target device has
decoded its address as the target of the current access. The 82443GX asserts
DEVSEL# based on the DRAM address range or AGP address range being accessed
by a PCI initiator. As an input it indicates whether any device on the bus has been
selected.
Frame: FRAME# is an output when the 82443GX acts as an initiator on the PCI Bus.
FRAME# is asserted by the 82443GX to indicate the beginning and duration of an
access. The 82443GX asserts FRAME# to indicate a bus transaction is beginning.
While FRAME# is asserted, data transfers continue. When FRAME# is negated, the
transaction is in the final data phase. FRAME# is an input when the 82443GX acts as
a PCI target. As a PCI target, the 82443GX latches the C/BE[3:0]# and the AD[31:0]
signals on the first clock edge on which it samples FRAME# active.
Initiator Ready: IRDY# is an output when 82443GX acts as a PCI initiator and an
input when the 82443GX acts as a PCI target. The assertion of IRDY# indicates the
current PCI Bus initiator's ability to complete the current data phase of the
transaction.
2-4
82443GX Host Bridge Datasheet