82443GX Datasheet, PDF (70/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller

Register Description
3.4
PCI-to-PCI Bridge Registers (Device 1)
The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register.
Note: When AGP_DIS = 0, the configuration space for device #1 is enabled, and the registers defined
below are accessible through the configuration mechanism defined in the first section of this
document.
Note:
When the AGP_DIS = 1, the configuration space for device #1 is disabled. All configuration cycles
(reads and writes) to device #1 of bus 0 will cause the master abort status bit for device #0/ bus 0 to
be set. Configuration read cycles will return data of all 1’s. Configuration write cycles will have no
effect on the registers.
Table 3-4. 82443GX Configuration Space—Device 1
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0F–17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–3Dh
3Eh
3F–FFh
Register
Symbol
VID1
DID1
PCICMD1
PCISTS1
RID1
—
SUBC1
BCC1
—
MLT1
HDR1
—
PBUSN
SBUSN
SUBUSN
SMLT
IOBASE
IOLIMIT
SSTS
MBASE
MLIMIT
PMBASE
PMLIMIT
—
BCTRL
—
Register Name
Vendor Identification
Device Identification
PCI Command Register
PCI Status Register
Revision Identification
Reserved
Sub-Class Code
Base Class Code
Reserved
Master Latency Timer
Header Type
Reserved
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Secondary Bus Master Latency Timer
I/O Base Address Register
I/O Limit Address Register
Secondary PCI-to-PCI Status Register
Memory Base Address Register
Memory Limit Address Register
Prefetchable Memory Base Address Reg.
Prefetchable Memory Limit Address Reg.
Reserved
Bridge Control Register
Reserved
Default
Value
8086h
71A1h
0000h
0220h
00h
00h
04h
06h
00h
00h
01h
00h
00h
00h
00h
00h
F0h
00h
02A0h
FFF0h
0000h
FFF0h
0000h
0
80h
00h
Access
RO
RO
R/W
RO, R/WC
RO
—
RO
RO
—
R/W
RO
—
RO
R/W
R/W
R/W
R/W
R/W
R/WC, RO
R/W
R/W
R/W
R/W
c
R/W
—
3-46
82443GX Host Bridge Datasheet