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82443GX Datasheet, PDF (5/128 Pages) Intel Corporation – Intel 440GX AGPset: 82443GX Host Bridge/Controller | |||
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Contents
1
Architectural Overview ...............................................................................................1-1
2
Signal Description ......................................................................................................2-1
2.1 Host Interface Signals...................................................................................2-1
2.2 DRAM Interface ............................................................................................2-3
2.3 PCI Interface (Primary) .................................................................................2-4
2.4 Primary PCI Sideband Interface ...................................................................2-6
2.5 AGP Interface Signals...................................................................................2-6
2.6 Clocks, Reset, and Miscellaneous ................................................................2-8
2.7 Power-Up/Reset Strap Options.....................................................................2-9
3
Register Description...................................................................................................3-1
3.1 I/O Mapped Registers ...................................................................................3-2
3.1.1 CONFADDâConfiguration Address Register..................................3-2
3.1.2 CONFDATAâConfiguration Data Register .....................................3-3
3.1.3 PM2_CTLâACPI Power Control 2 Control Register .......................3-4
3.2 PCI Configuration Space Access..................................................................3-4
3.2.1 Configuration Space Mechanism Overview .....................................3-5
3.2.2 Routing the Configuration Accesses to PCI or AGP ........................3-5
3.2.3 PCI Bus Configuration Mechanism Overview ..................................3-6
3.2.3.1 Type 0 Access ....................................................................3-6
3.2.3.2 Type 1 Access ....................................................................3-6
3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6
3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7
3.3 Host-to-PCI Bridge Registers (Device 0) ......................................................3-8
3.3.1 VIDâVendor Identification Register (Device 0).............................3-10
3.3.2 DIDâDevice Identification Register (Device 0) .............................3-10
3.3.3 PCICMDâPCI Command Register (Device 0) ..............................3-11
3.3.4 PCISTSâPCI Status Register (Device 0) .....................................3-12
3.3.5 RIDâRevision Identification Register (Device 0) ..........................3-13
3.3.6 SUBCâSub-Class Code Register (Device 0) ...............................3-13
3.3.7 BCCâBase Class Code Register (Device 0) ................................3-13
3.3.8 MLTâMaster Latency Timer Register (Device 0)..........................3-14
3.3.9 HDRâHeader Type Register (Device 0) .......................................3-14
3.3.10 APBASEâAperture Base Configuration Register (Device 0)........3-14
3.3.11 SVIDâSubsystem Vendor Identification Register (Device 0)........3-15
3.3.12 SIDâSubsystem Identification Register (Device 0).......................3-16
3.3.13 CAPPTRâCapabilities Pointer Register (Device 0) ......................3-16
3.3.14 NBXCFGâNBX Configuration Register (Device 0) .......................3-16
3.3.15 DRAMCâDRAM Control Register (Device 0) ...............................3-19
3.3.16 PAM[6:0]âProgrammable Attribute Map Registers
(Device 0).......................................................................................3-20
3.3.17 DRB[0:7]âDRAM Row Boundary Registers (Device 0) ................3-22
3.3.18 FDHCâFixed DRAM Hole Control Register (Device 0) ................3-24
3.3.19 MBSCâMemory Buffer Strength Control Register
(Device 0).......................................................................................3-24
3.3.20 SMRAMâSystem Management RAM Control Register
(Device 0).......................................................................................3-28
82443GX Host Bridge Datasheet
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