TDA5225 Datasheet, PDF (67/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

2.6.2 Polling Timer Unit
TDA5225
Functional Description
f_sys / 64
SPM
f_RT
Reference-Timer
(8 Bit)
SPM
On -Off -Timer
(14 Bit)
f_OnOff
SPM
Active-Idle Period Timer
(5 / 8 Bit)
No WU
Self-Polling-Mode (SPM)
FSM
Polling Mode
Figure 44 Polling Timer Unit
to
Master-Control-Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (f_sys/64) into the slower
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5225 is able to handle up to four different sets of configurations automatically.
However, the example and figure in this subsection only show up to two configuration
sets for the sake of clarity.
Data Sheet
67
V1.0, 2010-02-19