TDA5225 Datasheet, PDF (121/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Overview
Table 2 Register Overview and Reset Value (cont’d)
Register Short Name Register Long Name
Offset Address
D_SRC
D_EXTSLC
D_CHCFG
D_PLLINTC1
D_PLLFRAC0C1
D_PLLFRAC1C1
D_PLLFRAC2C1
D_PLLINTC2
D_PLLFRAC0C2
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
Sampe Rate Converter NCO Tune
33D_H
Externel Data Slicer Configuration
33E_H
Channel Configuration Register
358_H
PLL MMD Integer Value Register Channel 1
359_H
PLL Fractional Division Ratio Register 0 Channel 1 35A_H
PLL Fractional Division Ratio Register 1 Channel 1 35B_H
PLL Fractional Division Ratio Register 2 Channel 1 35C_H
PLL MMD Integer Value Register Channel 2
35D_H
PLL Fractional Division Ratio Register 0 Channel 2 35E_H
PLL Fractional Division Ratio Register 1 Channel 2 35F_H
PLL Fractional Division Ratio Register 2 Channel 2 360_H
PLL MMD Integer Value Register Channel 3
361_H
PLL Fractional Division Ratio Register 0 Channel 3 362_H
PLL Fractional Division Ratio Register 1 Channel 3 363_H
PLL Fractional Division Ratio Register 2 Channel 3 364_H
Reset Value
00_H
02_H
44_H
93_H
F3_H
07_H
09_H
13_H
F3_H
07_H
09_H
13_H
F3_H
07_H
09_H
Data Sheet
121
V1.0, 2010-02-19