TDA5225 Datasheet, PDF (141/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
UNUSED
7:6
PLLFCOMPC1 5
PLLFRAC2C1 4:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Fractional Spurii Compensation enable for Channel 1
0_B Disabled
1_B Enabled
Reset: 0_H
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
PLL MMD Integer Value Register Channel 2
A_PLLINTC2
PLL MMD Integer Value Register Channel 2



8186('

Offset
05D_H
3//,17&
Z
Reset Value
13_H

Field
Bits
UNUSED
7:6
PLLINTC2
5:0
Type
-
w
Description
UNUSED
Reset: 0_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 2
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 2
A_PLLFRAC0C2
PLL Fractional Division Ratio Register 0
Channel 2
Offset
05E_H

3//)5$&&
Z
Reset Value
F3_H

Data Sheet
141
V1.0, 2010-02-19