TDA5225 Datasheet, PDF (36/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
Notes:
1. The upper RF input level must stay well below the saturation level of the receiver (see
Chapter 2.4.6.4 Digital Automatic Gain Control Unit (AGC))
2. The lower RF input level must stay well above the noise level of the receiver
3. If IF Attenuation is trimmed, this has to be done before trimming of RSSI
4. If RSSI needs to be trimmed in a higher input power range the AGCGAIN must be set
accordingly
2.4.8 Digital Baseband (DBB) Receiver
From ASK/
FSK
Demodulator
8 to 16
samples
per chip
adjust_length
Matched Filter
RAW Data Slicer
for external
processing
SRC
bypass
fractional SRC
fs_out / fs_in = 0.5 … 1.0
MUX
SIGN
Data
Invert
DINVEXT
Data
Invert
Figure 15
DATA
(Sliced RAW Data for
external processing )
DATA_MATCHFIL
(Matched Filtered Data
for external processing )
Functional Block Diagram Digital Baseband Receiver
The digital baseband receiver comprises a matched data filter and a data slicer. The
received data signal is accessible via one of the port pins.
2.4.8.1 Data Filter
The data filter is a matched filter (MF). The frequency response of a matched filter has
ideally the same shape as the power spectral density (PSD) of the originally transmitted
signal, therefore the signal-to-noise ratio (SNR) at the output of the matched filter
becomes maximum. The input sampling rate of the baseband receiver has to be
Data Sheet
36
V1.0, 2010-02-19