TDA5225 Datasheet, PDF (59/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
with defined settings at a defined state. Otherwise the state machine may hang up.
Reconfigurations in HOLD Mode are faster, because there is no Start-Up sequence.
The following flowchart and explanation show and help to understand the internal
behavior of the Finite State Machine (FSM) in Run Mode Slave.
Hold == 0
1
Wait
Wait Till Startup
Has Finished
Startup Finished == 0
Startup Finished == 1
2
INIT
4
Hold
Ready for
reconfiguration
Hold == 1
3
Receive
Data Available
At Port Pin
No Change in
Operating Mode
Figure 37 Run Mode Slave
2.6.1.3 HOLD Mode
This state (item 4 in Figure 37) is used for fast reconfiguration of the chip in Run Mode
Slave. HOLD state can be reached after the Start-Up Sequencer and Initialization of the
chip have been completed and the chip is working in state 3. To reconfigure the chip the
SFR control bit HOLD must be set. After reconfiguration in this state the SFR control bit
HOLD must be cleared again. After leaving the HOLD state, the INIT state is entered and
the receiver can work with the new settings. Be aware that the time between changing
the configuration and reinitialization of the chip has to be at least 40us. Take note that
one SPI command for clearing the SFR control bit HOLD needs 24 bits or 12μs at an SPI
data rate of 2.0Mbit/s. The remaining 28μs must be guaranteed by the application.
FSM State ^{Data available at Port Pin}
Instruction Address Data Instruction Address Data
SPI Command
Write
CMC0 HOLD=1 Write x_CHCFG/ (sel. other
0x02
0x02
x_PLL.. channel)
HOLD
Instruction Address
Write
CMC0
0x02
Data
HOLD=0
12us @ 2. 0MHz
40 us
INIT
Data
available at
Port Pin
Figure 38 HOLD State Behavior (INITPLLHOLD disabled)
Data Sheet
59
V1.0, 2010-02-19