TDA5225 Datasheet, PDF (166/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
TOTIM2NCH 4
Type
w
UNUSED
3:1
w
XTALHPMS 0
w
Chip Mode Control Register 0
Description
Continue with next RF channel in Self Polling Mode after TOTIM
detected in Run Mode Self Polling. In case of single RF channel
application this means "continue with next Configuration" instead
of "continue with next RF channel".
0_B Continue with Configuration A in Self Polling Mode
1_B Continue with next RF channel in Self Polling Mode
Reset: 0_H
UNUSED
Reset: 2_H
XTAL High Precision Mode in Sleep Mode
0_B Disabled
1_B Enabled
Reset: 0_H
CMC0
Chip Mode Control Register 0
Offset
0A6_H

6'2+33(
1
Z

,1,73//
+2/'
Z

+2/'
Z

&/.287(
1
Z


0&6
Z
Reset Value
10_H

6/5;(1
Z

06(/
Z
Field
Bits
SDOHPPEN 7
INITPLLHOLD 6
HOLD
5
CLKOUTEN 4
Data Sheet
Type
w
w
w
w
Description
SDO High Power Pad Enable
0_B Normal
1_B High Power
Reset: 0_H
Init PLL after coming from HOLD (when new channel programmed).
This requires an additional Channel Hop Time before initialization of the
Digital Receiver.
0_B No init of PLL
1_B Init of PLL
Reset: 0_H
Holds the chip in the Register Configuration state (only in Run Mode
Slave)
0_B Normal Operation
1_B Jump into the Register Config state Hold
Reset: 0_H
CLK_OUT Enable
0_B Disabled
1_B Enable programmable clock output
Reset: 1_H
166
V1.0, 2010-02-19