TDA5225 Datasheet, PDF (114/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Overview
Table 1 Register Overview (cont’d)
Register Short Name Register Long Name
Offset Address
D_AFCK2CFG1
D_PMFUDSF
D_AGCSFCFG
D_AGCCFG0
D_AGCCFG1
D_AGCTHR
D_DIGRXC
D_ISUPFCSEL
D_PDECF
D_PDECSCFSK
D_PDECSCASK
D_MFC
D_SRC
D_EXTSLC
D_CHCFG
D_PLLINTC1
D_PLLFRAC0C1
D_PLLFRAC1C1
D_PLLFRAC2C1
D_PLLINTC2
D_PLLFRAC0C2
D_PLLFRAC1C2
D_PLLFRAC2C2
D_PLLINTC3
D_PLLFRAC0C3
D_PLLFRAC1C3
D_PLLFRAC2C3
AFC Integrator 2 Gain Register 1
330_H
Peak Memory Filter Up-Down Factor Register
331_H
AGC Start/Freeze Configuration Register
332_H
AGC Configuration Register 0
333_H
AGC Configuration Register 1
334_H
AGC Threshold Register
335_H
Digital Receiver Configuration Register
336_H
Image Supression Fc Selection Register
338_H
Pre Decimation Factor Register
339_H
Pre Decimation Scaling Register FSK Mode
33A_H
Pre Decimation Scaling Register ASK Mode
33B_H
Matched Filter Control Register
33C_H
Sampe Rate Converter NCO Tune
33D_H
Externel Data Slicer Configuration
33E_H
Channel Configuration Register
358_H
PLL MMD Integer Value Register Channel 1
359_H
PLL Fractional Division Ratio Register 0 Channel 1 35A_H
PLL Fractional Division Ratio Register 1 Channel 1 35B_H
PLL Fractional Division Ratio Register 2 Channel 1 35C_H
PLL MMD Integer Value Register Channel 2
35D_H
PLL Fractional Division Ratio Register 0 Channel 2 35E_H
PLL Fractional Division Ratio Register 1 Channel 2 35F_H
PLL Fractional Division Ratio Register 2 Channel 2 360_H
PLL MMD Integer Value Register Channel 3
361_H
PLL Fractional Division Ratio Register 0 Channel 3 362_H
PLL Fractional Division Ratio Register 1 Channel 3 363_H
PLL Fractional Division Ratio Register 2 Channel 3 364_H
Page Number
Table 2 Register Overview and Reset Value
Register Short Name Register Long Name
Offset Address
Appendix - Registers Chapter, Register Description
A_IF1
A_WURSSITH1
A_WURSSIBL1
IF1 Register
RSSI Wake-Up Threshold for Channel 1 Register
RSSI Wake-Up Blocking Level Low Channel 1
Register
016_H
01B_H
01C_H
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01D_H
A_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 01E_H
Reset Value
20_H
00_H
FF_H
00_H
00_H
Data Sheet
114
V1.0, 2010-02-19