TDA5225 Datasheet, PDF (127/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
WULOT
4:0
Type
w
Description
Wake-Up Level Observation Time
Min. 01h : Twulot = 1 * WULOTPS * 64 / Fsys
Max 1Fh : Twulot = 31 * WULOTPS * 64 / Fsys
Value 00h : Twulot = 32 * WULOTPS * 64 / Fsys
Reset: 00_H
AFC Limit Configuration Register
A_AFCLIMIT
AFC Limit Configuration Register

8186('

Offset
02A_H


$)&/,0,7
Z
Reset Value
02_H

Field
Bits
UNUSED
7:4
AFCLIMIT
3:0
Type
-
w
AFC/AGC Freeze Delay Register
Description
UNUSED
Reset: 0_H
AFC Frequency Offset Saturation Limit ==> 1...15 x 21.4 kHz
Min: 1h = +/- Fsys / 2^(22-12) Hz
Max: Fh = +/- 15 * Fsys / 2^(22-12) Hz
Reg. value 0h = 0 Hz - no AFC correction
Reset: 2_H
A_AFCAGCD
AFC/AGC Freeze Delay Register

Offset
02B_H
$)&$*&'
Z
Reset Value
00_H

Field
Bits
AFCAGCD 7:0
Type
w
Description
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00_H
Data Sheet
127
V1.0, 2010-02-19