TDA5225 Datasheet, PDF (39/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
2.4.9 Power Supply Circuitry
The chip may be operated within a 5 Volts or a 3.3 Volts environment.
VDDA
GNDA
GNDRF
P_ON
IN
Voltage Regulator
5 → 3.3 V
OUT
RX_RUN
Analog
Section
RF
Section
Figure 18 Power Supply
IN
Voltage Regulator
5 → 3.3 V
OUT
IN
Voltage Regulator
3.3 → 1.5 V
OUT
VDD5V
Digital-I/O
VDDD
Power-Up
Brownout
Detector
Reset- Internal
Circuit Reset
Digital-Core
VDDD1V5
GNDD
For operation within a 5 Volts environment (supply voltage range 1), the chip is supplied
via the VDD5V pin. In this configuration the digital I/O pads are supplied via VDD5V and
a 5 V to 3.3 V voltage regulator supplies the analog/RF section (only active in Run
Modes).
When operating within a 3.3 Volts environment (supply voltage range 2), the VDD5V,
VDDA and VDDD pins must be supplied. The 5 V to 3.3 V voltage regulators are inactive
in this configuration.
The internal digital core is supplied by an additional 3.3 V to 1.5 V regulator.
The regulators for the digital section are controlled by the signal at P_ON (Power On)
pin. A low signal at P_ON disables all regulators and set the IC in Power Down Mode. A
low to high transition at P_ON enables the regulators for the digital section and initiates
a power on reset. The regulator for the analog section is controlled by the Master Control
Unit and is active only when the RF section is active.
To provide data integrity within the digital units, a brownout detector monitors the digital
supply. In case a voltage drop of VDDD below approximately 2.45 V is detected a
RESET will be initiated.
Data Sheet
39
V1.0, 2010-02-19