TDA5225 Datasheet, PDF (131/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
PMFUP
6:4
UNUSED
3
PMFDN
2:0
Type
w
-
w
Description
Peak Memory Filter Attack (Up) Factor
000_B 2^-1
001_B 2^-2
010_B 2^-3
011_B 2^-4
100_B 2^-5
101_B 2^-6
110_B 2^-7
111_B 2^-8
Reset: 4_H
UNUSED
Reset: 0_H
Peak Memory Filter Decay (Down) Factor (additional to Attack
Factor)
000_B 2^-2
001_B 2^-3
010_B 2^-4
011_B 2^-5
100_B 2^-6
101_B 2^-7
110_B 2^-8
111_B 2^-9
Reset: 2_H
AGC Start/Freeze Configuration Register
A_AGCSFCFG
AGC Start/Freeze Configuration Register
Offset
032_H


8186('


$*&5(6$
7&&
Z


$*&)5((=(
Z
Reset Value
00_H


$*&67$57
Z
Field
Bits
UNUSED
7:6
AGCRESATC 5
C
Type
-
w
Description
UNUSED
Reset: 0_H
Enable AGC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0_B Disabled
1_B Enabled
Reset: 0_H
Data Sheet
131
V1.0, 2010-02-19