TDA5225 Datasheet, PDF (151/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
CLKOUT1
7:0
Type
w
Clock Divider Register 2
Description
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 00_H
CLKOUT2
Clock Divider Register 2

8186('

Offset
088_H


&/.287
Z
Reset Value
00_H

Field
Bits
UNUSED
7:4
CLKOUT2
3:0
RF Control Register
Type
-
w
Description
UNUSED
Reset: 0_H
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0_H
RFC
RF Control Register


8186('

Offset
089_H


5)2))
Z
Field
Bits
UNUSED
7:5
Data Sheet
Type
-
Description
UNUSED
Reset: 0_H
151
,)$77
Z
Reset Value
07_H

V1.0, 2010-02-19