TDA5225 Datasheet, PDF (17/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
2.4.2 Block Overview
The TDA5225 is separated into the following main blocks:
• RF / IF Receiver
• Crystal Oscillator and Clock Divider
• Sigma-Delta Fractional-N PLL Synthesizer
• ASK / FSK Demodulator incl. AFC, AGC and ADC
• RSSI Peak Detector
• Digital Baseband Receiver
• Power Supply Circuitry
• System Interface
• System Management Unit
Functional Description
2.4.3 RF/IF Receiver
The receiver path uses a double down conversion super-heterodyne/low-IF architecture,
where the first IF frequency is located around 10.7 MHz and the second IF frequency
around 274 kHz. For the first IF frequency an adjustment-free image frequency rejection
is realized by means of two low-side injected I/Q-mixers followed by a second order
passive polyphase filter centered at 10.7 MHz (PPF). The I/Q-oscillator signals for the
first down conversion are delivered from the PLL synthesizer. The frequency selection
in the first IF domain is done by an external CER filter (optionally by two, decoupled by
a buffer amplifier). For moderate or low cost applications, this ceramic filter can be
substituted by a simple LC Pi-filter or completely by-passed using the receiver as a
single down conversion low-IF scheme with 274 kHz IF frequency. The down conversion
to the second IF frequency is done by means of two high-side injected I/Q-mixers
together with an on-chip third order bandpass polyphase filter (PPF2 + BPF). The I/Q-
oscillator signals for the second down conversion are directly derived by division of two
from the crystal oscillator frequency. The bandwidth of the bandpass filter (BPF) can be
selected from 50 kHz to 300 kHz in 5 steps. For a frequency offset of -150 kHz to -120
kHz, the AFC (Automatic Frequency Control) function is mandatory. Activated AFC
option might require a longer preamble sequence in the receive data stream.
The receiver enable signal (RX_RUN) can be offered at each of the port pins to control
external components. Whenever the receiver is active, the RX_RUN output signal is
active. Active high or active low is configurable via PPCFG2 register.
Data Sheet
17
V1.0, 2010-02-19