TDA5225 Datasheet, PDF (150/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
RXRUNPP2C 2
Type
w
RXRUNPP2B 1
w
RXRUNPP2A 0
w
Clock Divider Register 0
Description
RXRUN Active Level on PP2 for Configuration C
0_B Active Low
1_B Active High
Reset: 1_H
RXRUN Active Level on PP2 for Configuration B
0_B Active Low
1_B Active High
Reset: 1_H
RXRUN Active Level on PP2 for Configuration A
0_B Active Low
1_B Active High
Reset: 1_H
CLKOUT0
Clock Divider Register 0

Offset
086_H
&/.287
Z
Reset Value
0B_H

Field
Bits
CLKOUT0
7:0
Type
w
Clock Divider Register 1
Description
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0B_H
CLKOUT1
Clock Divider Register 1

Offset
087_H
&/.287
Z
Reset Value
00_H

Data Sheet
150
V1.0, 2010-02-19