TDA5225 Datasheet, PDF (58/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
Reset
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == 0
Bit:MSEL == 0
Sleep Mode
Chip is idle
Init
Initialize RX-Part
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Bit:SLRXEN == 1
Bit:MSEL == 0
Run Mode
Slave
Bit:SLRXEN == 0
or
Bit:MSEL == 1
Chip is permanently
active
Bit:SLRXEN == X
Bit:MSEL == 1
Bit:SLRXEN == X
Bit:MSEL == 0
Init
Bit:SLRXEN == 1
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 0
Bit:SLRXEN == X
Bit:MSEL == 0
ToTim Timeout== X
Bit:SLRXEN == X
Bit:MSEL == 1
EOM found == 1
Initialize RX-Part
Bit:SLRXEN == X
Bit:MSEL == 1
Self Polling
Mode
Chip is periodically active
and searching for
WU criteria
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 1
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 0
Bit:SLRXEN == X
Bit:MSEL == 1
WUC found == 1
Run Mode
Self Polling
Chip is permanently
ac t iv e
Bit:SLRXEN == X
Bit:MSEL == 1
ToTim Timeout == 0
Figure 36 Global State Diagram
2.6.1.2 Run Mode Slave (RMS)
In Run Mode Slave, the receiver is able to continuously scan for incoming data streams.
Detection and validation of a wake-up criterion are not performed.
The transparent data stream can be processed externally by the Application Controller
(see Chapter 2.5.1.2 Data Interface).
Run Mode Slave is entered by setting SFR CMC0 bits MSEL to 0 and SLRXEN to 1.
Configurations are switched via SFR bit group MCS in the CMC0 register. The RF
channel in use can be selected in the x_CHCFG register, the frequency selection is
defined by SFRs x_PLLINTCy, x_PLLFRAC0Cy, x_PLLFRAC1Cy, x_PLLFRAC2Cy,
where x = A, B, C or D and y = 1, 2 or 3.
The configuration may be changed only in SLEEP or in HOLD Mode before returning to
the previously selected operation mode. This is necessary to restart the state machine
Data Sheet
58
V1.0, 2010-02-19