TDA5225 Datasheet, PDF (144/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
A_PLLFRAC1C3
PLL Fractional Division Ratio Register 1
Channel 3
Offset
063_H

3//)5$&&
Z
Reset Value
07_H

Field
Bits
PLLFRAC1C3 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07_H
PLL Fractional Division Ratio Register 2 Channel 3
A_PLLFRAC2C3
PLL Fractional Division Ratio Register 2
Channel 3
Offset
064_H




8186('
3//)&20
3&

Z
3//)5$&&
Z
Reset Value
09_H

Field
Bits
UNUSED
7:6
PLLFCOMPC3 5
PLLFRAC2C3 4:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Fractional Spurii Compensation enable for Channel 3
0_B Disabled
1_B Enabled
Reset: 0_H
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
Special Function Register Page Register
Data Sheet
144
V1.0, 2010-02-19