TDA5225 Datasheet, PDF (158/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
UNUSED
7:5
SPMAP
4:0
Type
-
w
Description
UNUSED
Reset: 0_H
Self Polling Mode Active Periods value
Min: 01h = 1 (Master) Period
Max: 1Fh = 31(Master) Periods
Reg. value 00h = 32 (Master) Periods
Reset: 01_H
Self Polling Mode Idle Periods Register
SPMIP
Self Polling Mode Idle Periods Register

Offset
097_H
630,3
Z
Field
SPMIP
Bits
Type Description
7:0
w
Self Polling Mode Idle Periods value
Min: 01h = 1 (Master) Period
Max: FFh = 255 (Master) Periods
Reg. value 00h = 256 (Master) Periods
Reset: 01_H
Self Polling Mode Control Register
Reset Value
01_H

SPMC
Self Polling Mode Control Register

8186('

Offset
098_H

Field
Bits
UNUSED
7:3
Type
-
Description
UNUSED
Reset: 00_H

630$,(1
Z
Reset Value
00_H


8186('
Z
Data Sheet
158
V1.0, 2010-02-19