TDA5225 Datasheet, PDF (170/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
RSSIPRX
7:0
Type
rc
ADC Result High Byte Register
Description
RSSI Peak Level during Receiving
Tracking is active when Digital Receiver is enabled
Set at higher peak levels than stored
Cleared at Reset and SPI read out
Reset: 00_H
ADCRESH
ADC Result High Byte Register

Offset
0AE_H
$'&5(6+
UF
Reset Value
00_H

Field
Bits
ADCRESH 7:0
Type
rc
ADC Result Low Byte Register
Description
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00_H
ADCRESL
ADC Result Low Byte Register

8186('

Offset
0AF_H


$'&(2&
U
Field
Bits
UNUSED
7:3
ADCEOC
2
Type
-
r
Description
UNUSED
Reset: 00_H
ADC End of Conversion detected
0_B not detected
1_B detected
Reset: 0_H
Reset Value
00_H


$'&5(6/
U
Data Sheet
170
V1.0, 2010-02-19