TDA5225 Datasheet, PDF (143/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
PLLFRAC2C2 4:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
PLL MMD Integer Value Register Channel 3
A_PLLINTC3
PLL MMD Integer Value Register Channel 3



8186('

Offset
061_H
3//,17&
Z
Reset Value
13_H

Field
Bits
UNUSED
7:6
PLLINTC3
5:0
Type
-
w
Description
UNUSED
Reset: 0_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 3
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 3
A_PLLFRAC0C3
PLL Fractional Division Ratio Register 0
Channel 3
Offset
062_H

3//)5$&&
Z
Reset Value
F3_H

Field
Bits
PLLFRAC0C3 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 3
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3_H
PLL Fractional Division Ratio Register 1 Channel 3
Data Sheet
143
V1.0, 2010-02-19