TDA5225 Datasheet, PDF (156/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
RSSIOFFS 7:0
RSSI Slope Register
Type
w
Description
RSSI Offset Compensation Value
Min: 00h= -256
Max: FFh= 254
Reset: 80_H
RSSISLOPE
RSSI Slope Register

Offset
091_H
566,6/23(
Z
Reset Value
80_H

Field
Bits
RSSISLOPE 7:0
Type
w
Interrupt Mask Register 0
Description
RSSI Slope Compensation Value (Multiplication Value)
Multiplication Factor = RSSISLOPE * 2^-7
Min: 00h= 0.0
Max: FFh= 1.992
Reset: 80_H
IM0
Interrupt Mask Register 0


8186('

Offset
094_H


,0:8%
Z
8186('

Reset Value
00_H


,0:8$
Z
Field
Bits
UNUSED
7:5
IMWUB
4
Type
-
w
Description
UNUSED
Reset: 0_H
Mask Interrupt on "Wake-up" for Configuration B
0_B Interrupt enabled
1_B Interrupt disabled
Reset: 0_H
Data Sheet
156
V1.0, 2010-02-19