TDA5225 Datasheet, PDF (139/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
NOC
MT
Bits
Type Description
3:2
w
Number of Channels (Run Mode Slave / Self Polling Mode - Run
Mode Self Polling)
00_B Channel 1 / Channel 1
01_B Channel 1 / Channel 1
10_B Channel 2 / Channel 1 + 2
11_B Channel 3 / Channel 1 + 2 + 3
Reset: 1_H
1:0
w
Modulation Type (Run Mode Slave / Self Polling Mode - Run Mode
Self Polling)
00_B ASK / ASK - ASK
01_B FSK / FSK - FSK
10_B ASK / FSK - ASK
11_B FSK / ASK - FSK
Reset: 0_H
PLL MMD Integer Value Register Channel 1
A_PLLINTC1
PLL MMD Integer Value Register Channel 1



%$1'6(/
Z
Offset
059_H
3//,17&
Z
Reset Value
93_H

Field
Bits
BANDSEL
7:6
PLLINTC1
5:0
Type
w
w
Description
Frequency Band Selection
00_B not used
01_B 915MHz/868MHz
10_B 434MHz
11_B 315MHz
Reset: 2_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0
Channel 1
Offset
05A_H
Reset Value
F3_H
Data Sheet
139
V1.0, 2010-02-19