TDA5225 Datasheet, PDF (22/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
Recommended Trimming Procedure
• Set the registers XTALCAL0 and XTALCAL1 to the expected nominal values
• Set the TDA5225 to Run Mode Slave
• Wait for 0.5ms minimum
• Trim the oscillator by increasing and decreasing the values of XTALCAL0/1
• Register changes larger than 1 pF are automatically handled by the TDA5225 in 1 pF
steps
• After the Oscillator is trimmed, the TDA5225 can be set to SLEEP mode and keeps
these values during SLEEP mode
• Add the settings of XTALCAL0/1 to the configuration. It must be set after every power
up or brownout!
Using the High Precision Mode
As discussed earlier, the TDA5225 allows the crystal oscillator to be trimmed by the use
of internal trim capacitors. It is also possible to use the trim functionality to compensate
temperature drift of crystals.
During Run Mode (always when the receiver is active) the capacitors are automatically
connected and the oscillator is working in the High Precision Mode.
On entering SLEEP Mode, the capacitors are automatically disconnected to save
power.
If the High Precision Mode is also required for SLEEP Mode, the automatic disconnec-
tion of trim capacitors can be avoided by setting XTALHPMS to 1 (enable XTAL High
Precision Mode during SLEEP Mode).
External Clock Generation Unit
A built in programmable frequency divider can be used to generate an external clock
source out of the crystal reference. The 20 bit wide division factor is stored in the
registers CLKOUT0, CLKOUT1 and CLKOUT2. The minimum value of the
programmable frequency divider is 2. This programmable divider is followed by an
additional divider by 2, which generates a 50% duty cycle of the CLK_OUT signal. So
the maximum frequency at the CLK_OUT signal is the crystal frequency divided by 4.
The minimum CLK_OUT frequency is the crystal frequency divided by 2²¹.
To save power, this programmable clock signal can be disabled by the SFR control bit
CLKOUTEN. In this case the external clock signal is set to low.
Data Sheet
22
V1.0, 2010-02-19