TDA5225 Datasheet, PDF(113/176 Page) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

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TDA5225 Datasheet, PDF (113/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

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TDA5225

Appendix

Table 1 Register Overview (contâd)

Offset Address

C_PDECSCASK

C_MFC

C_SRC

C_EXTSLC

C_CHCFG

C_PLLINTC1

C_PLLFRAC0C1

C_PLLFRAC1C1

C_PLLFRAC2C1

C_PLLINTC2

C_PLLFRAC0C2

C_PLLFRAC1C2

C_PLLFRAC2C2

C_PLLINTC3

C_PLLFRAC0C3

C_PLLFRAC1C3

C_PLLFRAC2C3

D_IF1

D_WURSSITH1

D_WURSSIBL1

Pre Decimation Scaling Register ASK Mode

23BH

Matched Filter Control Register

23CH

Sampe Rate Converter NCO Tune

23DH

Externel Data Slicer Configuration

23EH

Channel Configuration Register

258H

PLL MMD Integer Value Register Channel 1

259H

PLL Fractional Division Ratio Register 0 Channel 1 25AH

PLL Fractional Division Ratio Register 1 Channel 1 25BH

PLL Fractional Division Ratio Register 2 Channel 1 25CH

PLL MMD Integer Value Register Channel 2

25DH

PLL Fractional Division Ratio Register 0 Channel 2 25EH

PLL Fractional Division Ratio Register 1 Channel 2 25FH

PLL Fractional Division Ratio Register 2 Channel 2 260H

PLL MMD Integer Value Register Channel 3

261H

PLL Fractional Division Ratio Register 0 Channel 3 262H

PLL Fractional Division Ratio Register 1 Channel 3 263H

PLL Fractional Division Ratio Register 2 Channel 3 264H

IF1 Register

316H

RSSI Wake-Up Threshold for Channel 1 Register 31BH

RSSI Wake-Up Blocking Level Low Channel 1

31CH

D_WURSSIBH1

RSSI Wake-Up Blocking Level High Channel 1

31DH

D_WURSSITH2

D_WURSSIBL2

RSSI Wake-Up Threshold for Channel 2 Register 31EH

RSSI Wake-Up Blocking Level Low Channel 2

31FH

D_WURSSIBH2

RSSI Wake-Up Blocking Level High Channel 2

320H

D_WURSSITH3

D_WURSSIBL3

RSSI Wake-Up Threshold for Channel 3 Register 321H

RSSI Wake-Up Blocking Level Low Channel 3

322H

D_WURSSIBH3

RSSI Wake-Up Blocking Level High Channel 3

323H

D_WULOT

D_AFCLIMIT

D_AFCAGCD

D_AFCSFCFG

D_AFCK1CFG0

D_AFCK1CFG1

D_AFCK2CFG0

Wake-Up on Level Observation Time Register

AFC Limit Configuration Register

AFC/AGC Freeze Delay Register

AFC Start/Freeze Configuration Register

AFC Integrator 1 Gain Register 0

AFC Integrator 1 Gain Register 1

AFC Integrator 2 Gain Register 0

325H

32AH

32BH

32CH

32DH

32EH

32FH

Page Number

Data Sheet

113

V1.0, 2010-02-19

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