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TDA5225 Datasheet, PDF (140/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver | |||
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TDA5225
Appendix
Register Description
3//)5$&&
Z
Field
Bits
PLLFRAC0C1 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1
Channel 1
Offset
05BH
3//)5$&&
Z
Reset Value
07H
Field
Bits
PLLFRAC1C1 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2
Channel 1
Offset
05CH
8186('
3//)&20
3&
Z
3//)5$&&
Z
Reset Value
09H
Data Sheet
140
V1.0, 2010-02-19
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