TDA5225 Datasheet, PDF (48/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
2.5.2 Digital Output Pins
As long as the P_ON pin is high, all digital output pins operate as described. If the P_ON
pin is low, all digital output pins are switched to high impedance mode.
The digital outputs PP0, PP1, PP2 and PP3 are configurable, where each of the signals
CLK_OUT, RX_RUN, NINT, a LOW level (GND) and a HIGH level, DATA and
DATA_MATCHFIL can be routed to any of the four output pins. There is only one
exception, CLK_OUT is not available on PP3. The default configuration for these four
output pins can be seen in Table 1.
Each port pin can be inverted by usage of PPCFG2 register.
The RX_RUN signal is active high for all Configurations by default. It can be deactivated
for every Configuration separately. Every PPx can be configured with an individual
RX_RUN setup. This can be set in RXRUNCFG0 and RXRUNCFG1 registers.
Interfacing to 3.3V Logic:
The TDA5225 is able to interface directly to a 3.3V logic, when chip is operated in 3.3V
environment.
Interfacing to 5V Logic:
The TDA5225 is able to interface directly to a 5V logic, when chip is operated in 5V
environment.
EMC Reduction of Digital I/Os:
Because electromagnetic distortion generated by digital I/Os may interfere with the high
sensitivity radio receiver, it is recommended that all inputs are filtered by adding an RC
low pass circuit.
2.5.3 Interrupt Generation Unit
The TDA5225 is able to signal interrupts (NINT signal) to the external Application
Controller on one of the PPx port pins (for further details see Chapter 2.5.2 Digital
Output Pins). The Interrupt Generation Unit receives all possible interrupts and sets the
NINT signal based on the configuration of the Interrupt Mask registers (IM0 and IM1).
The Interrupt Status registers (IS0 and IS1) are set from the Interrupt Generation Unit,
depending on which interrupt occurred. The polarity of the interrupt can be changed in
the PPCFG2 register. Please note that during power up and brownout reset, the polarity
of NINT signal is always as described in Chapter 2.4.9.2 Chip Reset.
A Reset event has the highest priority. It sets all bits in the Status registers to “1” and
sets the interrupt signal to “0”. The first interrupt after the Reset event will clear the Status
registers and will set the interrupt signal to “1”, even if this interrupt is masked.
An WU interrupt clears the complementary flags for WU.
Data Sheet
48
V1.0, 2010-02-19