TDA5225 Datasheet, PDF (54/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
The SPI also includes a safety feature by which the checksum is calculated with an
XOR operation from the address and the data when writing SFR registers. The
checksum is in fact an XOR of the data 8-bitwise after every 8 bits of the SPI write
command. The calculated checksum value is automatically written in the SPICHKSUM
register and can be compared with the expected value. After the SPICHKSUM register
is read, its value is cleared.
In case of an SPI Burst Write frame, a checksum is calculated from the SPI start address
and consecutive data fields.
enable every 8 bit
SPI shift register
XOR
Checksum SFR read/clear
Figure 32 SPI Checksum Generation
Table 4
Instruction Set
Instruction
Description
Instruction Format
WR
Write to chip
0000 0010
RD
Read from chip
0000 0011
WRB
Write to chip in Burst mode 0000 0001
RDB
Read from chip in Burst mode 0000 0101
Data Sheet
54
V1.0, 2010-02-19