TDA5225 Datasheet, PDF (134/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Appendix
Register Description
Field
Bits
AGCTUP
7:4
AGCTLO
3:0
Type
w
w
Description
AGC Upper Attack Threshold [dB]
AGC Upper Threshold = A_AGCCFG1.AGCTHOFFS + 25.6 +
AGCTUP*1.6
Reset: 0_H
AGC Lower Attack Threshold [dB]
AGC Lower Threshold = A_AGCCFG1.AGCTHOFFS + AGCTLO*1.6
Reset: 8_H
Digital Receiver Configuration Register
A_DIGRXC
Digital Receiver Configuration Register


,1,7'5;
(6
Z
8186('
Z
Offset
036_H

Reset Value
40_H

',19(;7
Z

$$)%<3
Z

$$))&6(
/
Z
Field
Bits
INITDRXES 7
UNUSED
6:3
DINVEXT
2
AAFBYP
1
AAFFCSEL 0
Type
w
w
w
w
w
Description
Init the Digital Receiver at EOM signal (e.g. for initialization of the
Peak Memory Filter)
0_B Disabled
1_B Enabled
Reset: 0_H
UNUSED
Reset: 8_H
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0_B Not inverted
1_B Inverted
Reset: 0_H
Anti-Alliasing Filter Bypass for RSSI pin
0_B Not bypassed
1_B Bypassed
Reset: 0_H
Anti-Alliasing Filter Corner Frequency Select
0_B 40 kHz
1_B 80 kHz
Reset: 0_H
Image Supression Fc Selection Register
Data Sheet
134
V1.0, 2010-02-19