TDA5225 Datasheet, PDF (51/176 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5225
Functional Description
2.5.4 Digital Control (4-wire SPI Bus)
The control interface used for device control is a 4-wire SPI interface.
• NCS - select input, active low
• SDI - data input
• SDO - data output
• SCK - clock input: Data bits on SDI are read in at rising SCK edges and written out
on SDO at falling SCK edges.
Level definition:
logic 0 = low voltage level
logic 1 = high voltage level
Note for non-Burst modes: It is possible to send multiple frames while the device is
selected. It is also possible to change the access mode while the device is selected by
sending a different instruction.
Note: In all bus transfers MSB is sent first.
To read from the device, the SPI master has to select the SPI slave unit first. Therefore,
the master must set the NCS line to low. After this, the instruction byte and the address
byte are shifted in on SDI and stored in the internal instruction and address register. The
data byte at this address is then shifted out on SDO. After completing the read operation,
the master sets the NCS line to high.
NCS
Frame
1
81
81
8
SCK
Instruction
Register Address
SDI
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
high impedance Z
SDO
D7 D6 D5 D4 D3 D2 D1 D0
Frame
1
81
81
8
Instruction
Register Address
I7 I6 I5 I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
D7 D6 D5 D4 D3 D2 D1 D0
Figure 28 Read Register
Data Sheet
51
V1.0, 2010-02-19