GDC21D003 Datasheet, PDF (75/77 Pages) Hynix Semiconductor – VSB Receiver

Timing Specification
SYMCLK
t_CRH
NRESET
t_IPL
POWER
POWER
ALL IN/OUT
Not Valid
SYMCLK
Input
Output
Output
Figure 7.1 Clock Reset Stabilization Timing
t_CP
t_IS t_IH
t_OD1
t_OD2
Figure 7.2 Input and Output Timing
GDC21D003
Valid
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