GDC21D003 Datasheet, PDF (41/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
6.3.6 Polarity Decision
It decides input signal polarity after it finds Data
Segment Sync timing input from transmitter and
checks Data Segment Sync pattern. Data Segment
Sync pattern input from transmitter is (1,0,0,1).
Therefore when Data Segment Sync pattern of
transmitted signal is (1,0,0,1), baseband signal has
positive polarity, and when (0,1,1,0), it has
negative polarity. In this block, input Data Segment
Sync pattern is checked and output signal is
generated by this result. Then it is sent to internal
Polarity Correction and demodulator. Also,
regardless of inputted Data Segment Sync pattern,
through I²C bus, DATAPOLP and DATAPOLN are
decided. The output of Polarity Decision, DAPOLP
and DATAPOLN are shown in Table 6.3.2. On the
other hand, DATAPOLN signal can be read
through I²C bus.(DATAPOLN in I²C bus register8)
Figure 6.3.9 describes the connection of
DATAPOLP & DATAPOLN which is output of
chip and Demodulator chip.
Table 6.3.2 DATAPOLP & DATAPOLN Output
Before Data Segment Sync Lock
Positive polarity
DATAPOLP
‘0’
Negative polarity
‘0’
PolarityW : ‘0’
Positive polarity
‘1’
(I²C bus register4)
After Data Segment
Negative polarity
‘0’
Sync Lock
Polarity : ‘0’
‘1’
PolarityW : ‘1’
(I²C bus register4)
(I²C bus register4)
Polarity : ‘1’
‘0’
(I²C bus register4)
DATAPOLN
‘0’
‘0’
‘0’
‘1’
‘0’
‘1’
LA7785M
(SANYO)
23
POLP
22
POLN
44
DATAPOLP
GDC21D003
43
(LG)
DATAPOLN
Figure 6.3.9 Polarity Signal I/F Circuit
42