GDC21D003 Datasheet, PDF (34/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
6.2 Clock Divider
VSB receiver(GDC21D003) can use external
VCXO which outputs symbol frequency and its
multiple frequency because it has internal clock
divider. Multiples can be 2 times. Also, this block
has 2 output signals, CLKFS and ADCCLK.
CLKFS is used as symbol clock for DTV
transmitter, ADCCLK is used as A/D converter’s
clock when external A/D converter is used for
digital input. The phase of ADCCLK against
CLKFS can vary through I²C bus. When external
VCXO output frequency is 2 times(21.52MHz) of
symbol frequency, the output frequency of
ADCCLK signal becomes the same as symbol
frequency(10.76MHz) or 2 times of symbol
frequency(21.52MH).
ADCCLK should be set through I²C bus according
to output frequency of external VCXO. The setting
of each case is described in following tale 6.2.1.
Frequency of
external
VCXO
10.76MHz
10.76MHz
10.76MHz
10.76MHz
21.52MHz
21.52MHz
21.52MHz
21.52MHz
Table 6.2.1 Register Setting for Clock Divider
VCXOSEL[1:0]
(in I²C bus
register5)
“00”
“00”
“00”
“00”
“01”
“01”
“01”
“01”
ADCCLKPH
(in I²C bus
register0)
ADCCLKSEL
(I²C bus
register0)
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘1’
‘1’
‘0’
‘0’
‘0’
‘1’
‘1’
‘0’
‘1’
‘1’
ADCCLK
(phase
regarding
CLKFS)
10.76MHz
(phase: 180^o)
10.76MHz
(phase: 180^o)
10.76MHz
(phase: 0^o)
10.76MHz
(phase: 0^o)
21.52MHz
(phase: 180^o)
10.76MHz
(phase: 180^o)
21.52MHz
(phase: 0^o)
10.76MHz
(phase: 0^o)
CLKFS
10.76MHz
10.76MHz
10.76MHz
10.76MHz
10.76MHz
10.76MHz
10.76MHz
10.76MHz
35