GDC21D003 Datasheet, PDF (38/77 Pages) Hynix Semiconductor – VSB Receiver

6.3.2 DC Reduction
Current DTV transmission system uses pilot for
restoration of carrier signal. Inserted DC value at
transmitter is transformed into pilot in frequency
domain. In receiver, A/D is used to convert
GDC21D003
baseband analog signal that completed the
demodulation of RF signal into digital signal, A/D
output has the same DC value inserted from
transmitter. Also DC components arise through
various analog processing.
Input Selection
10
+
-
10
10
Accumulator
10
Multiplexer
DC Reduction
DChold
DCbypass
Figure 6.3.4 The Block Diagram of DC Reduction
Figure 6.3.4 is block diagram of DC Reduction.
Output of Input Selection is sent to DC Reduction
block and removes pilot as well as all DCs in
analog system. And DC value is calculated from all
data of input signal.
Through I²C bus this block can be bypassed and
DC value doesn’t be updated from current state.
Among I²C bus control signals, if DC bypass
signal(in I²C bus register0) is ‘0’, DC removed
signal is output, and if it is ‘1’, input signal is
bypassed and output. Also, when DChold
signal(in I²C bus register0) is ‘0’, DC value is
calculated using continuously input signals, when it
is ‘1’, DC value at the moment is saved without
updating DC value. Calculated DC value can be
read through I²C bus. (DCvalue[7:0] in I²C bus
register address6)
6.3.3 Auto Gain Control(AGC)
There are 2 AGC modes currently used, one is
Non-coherent AGC mode and the other is Coherent
AGC mode. Figure 6.3.5 is the block diagram of
AGC. Non-coherent AGC mode is performed
during initialization state and before finding the
Data Segment Sync interval in receiver. During
initialization state, it increases Gain continuously
to take the maximum value.(GUP = ‘1’ during
initialization state). Also, since at the moment of
reset completion, received signal has the maximum
gain, it is highly possible that A/D converter output
has either maximum or minimum value. A/D
converter output can also have either maximum or
minimum value from too much noise within
channel. When input signal value has
maximum/minimum value for 8 symbols in a row,
control signal (GDN = ‘1’ during 2 symbols) is
generated to reduce system gain. Non-coherent
AGC mode doesn’t stop before it finds timing of
Data Segment Sync signal. Coherent AGC mode
calculates the average of input signals and controls
the GUP/GDN signal so that this average value can
have the desired value.
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