GDC21D003 Datasheet, PDF (4/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
6.5 Phase Tracker .................................................................................................................. 56
6.5.1 Error Detection ............................................................................................................ 57
6.5.2 Gain & Offset Loop...................................................................................................... 58
6.5.3 Phase Loop ................................................................................................................. 58
6.5.4 I2C Bus I/F .................................................................................................................. 59
6.6 Channel Decoder.............................................................................................................. 60
6.6.1 12 Symbol Intrasegment Deinterleaver....................................................................... 61
6.6.2 Segment Sync Suspension ......................................................................................... 61
6.6.3 Viterbi Decoder............................................................................................................ 62
6.6.4 Symbol-to-Byte Converter........................................................................................... 64
6.6.5 Convolutional Deinterleaver ........................................................................................ 65
6.6.6 Reed-Solomon Decoder.............................................................................................. 65
6.6.7 Data Derandomizer ..................................................................................................... 66
6.6.8 I/F to Transport Demultiplexer..................................................................................... 67
6.7 PLL.................................................................................................................................... 74
7. Electrical Characteristics ...................................................................................................... 75
8. Package Dimensions ............................................................................................................. 77
9. Application Notes .................................................................................................................. 78
Figures
Figure 3.1 Functional Block Diagram .............................................................................. 10
Figure 5.1.1 I²C Write Operation Example .......................................................................... 17
Figure 5.1.2 I²C Read Operation Example .......................................................................... 18
Figure 6.1.1 The Block Diagram of ADC ............................................................................. 29
Figure 6.1.2 Timing Diagram of ADC .................................................................................. 32
Figure 6.1.3 ADC Application Circuit ................................................................................... 33
Figure 6.1.4 Equivalent Circuits .......................................................................................... 34
Figure 6.3.1 The Block Diagram of Input Selection ............................................................ 36
Figure 6.3.2 Digital Input Setting Up & Chip I/F Circuit(1) .................................................. 37
Figure 6.3.3 Digital Input Setting Up & Chip I/F Circuit(2) .................................................. 38
Figure 6.3.4 The Block Diagram of DC Reduction .............................................................. 39
Figure 6.3.5 The Block Diagram of AGC ............................................................................ 40
Figure 6.3.6 AGC Signal I/F for DTV System ..................................................................... 40
Figure 6.3.7 The Block Diagram of Polarity Correction ....................................................... 41
Figure 6.3.8 The Block Diagram of Data Segment Sync Recovery .................................... 41
Figure 6.3.9 Polarity signal I/F Circuit ................................................................................. 42
Figure 6.3.10 Timing Recovery Block .................................................................................... 43
Figure 6.3.11 Timing Recovery I/F Circuit(1) ......................................................................... 44
Figure 6.3.12 Timing Recovery I/F Circuit(2) ......................................................................... 45
Figure 6.3.13 Field Sync Structure ........................................................................................ 46
Figure 6.3.14 The Block Diagram of Field Sync Recovery .................................................... 46
Figure 6.3.15 Comb Filter Block ............................................................................................ 48
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