GDC21D003 Datasheet, PDF (73/77 Pages) Hynix Semiconductor – VSB Receiver

6.7 PLL
The 4-times multiplexing scheme is used in the
256-tap filter. The PLL is used for generating the
4-times multiplying clock(CLK4EQ). Basically a
little jitter between SYMCLK and CLK4EQ may
occur. The clock skew due to the jitter can result in
abnormal operation in the paths related to both two
clocks. We used the following method to make
GDC21D003
robust design against the clock skew. The
SYMCLK is delayed by 4 CLK4EQ-clock cycles.
The delayed clock is CLKEQ. Then the skew
between CLKEQ and CLK4EQ is fixed in spite of
the jitter of PLL. To fix skew is very useful
because it is difficult to estimate the accurate
amount of jitter. The scheme is shown in figure
6.7.1.
SYMCLK
Clock Delay
4X-PLL
CLK4EQ
CLKEQ
Equalizer
Control
Coefficient-
Update
Filter
Figure 6.7.1 Clock Scheme
74