GDC21D003 Datasheet, PDF (53/77 Pages) Hynix Semiconductor – VSB Receiver

6.4.6 I²C Bus I/F
I Channel
Input
Symbols
10.76
MS/sec.
GDC21D003
256 tap adaptive filter
I²C Control
Control
Equalized
I Channel
Output
Training
Sequence
M
U
X
Slicer
10.76
MS/sec.
-
Σ₊
I²C BUS
Figure 6.4.6 I²C Bus I/F
The adaptive filter is able to initialize and freeze its
coefficients through register33[2](InitEQI2) bit and
register33[3](nFreezeEQI2) bit. The control block
located at the front of filter controls the estimated
error value according to each operating mode and
sends it to the adaptive filter. These bits are in the
table
6.4.1.
For
example,
if
register33[3](nFreezeEQI2) bit is set to “low”,
Equalizer Control block forces error value to be ‘0’,
which makes the coefficients of the filter
unchanged. The equalizer supports three different
step-sizes; the smallest, the middle, and the largest
step size. The difference is converging time and
remaining error. If the largest step-size is selected,
equalizer converges fast but the remaining error is
large. And if the smallest step-size is selected
equalizer converges slowly but the remaining error
is small. The decision directed mode can be used
for moving ghost by just setting nAdtOnDataI2.
When this signal is low, the decision directed
equalization is ON. When this pin is high, the
decision directed equalization is OFF.
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