GDC21D003 Datasheet, PDF (37/77 Pages) Hynix Semiconductor – VSB Receiver

LA 7785M
De(SmAoNdYuOla)tor
A/D
GDC21D003
126
INN
125
INP
DIN[9:0]
41
SYMCLK
18
CLKFS
GDC21D003
VCXO
(NOTE) - Regarding external VCXO output frequency, VCXOSEL[1:0] should be set as Table 6.2.1.
- Since internal ADC is used, frequency and phase of ADCCLK that is its input clock should be set as Table 6.2.1.
- Digital input signal path should be set as Table 6.3.1 to use external ADC output.
- If VCXO output frequency is equal to symbol frequency, VCXO(pin12) can be connected to GND, and
SYMCLK(pin41), A/D clock, and VCXO output can be connected directly.
Figure 6.3.3 I/F Circuit Diagram between VSB Receiver & Demodulator (External A/D Input)
38