GDC21D003 Datasheet, PDF (6/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
Tables
Table 6.2.1
Table 6.3.1
Table 6.3.2
Table 6.3.3
Table 6.3.4
Table 6.3.5
Table 6.4.1
Table 6.4.2
Table 6.5.1
Table 6.5.2
Table 6.6.1
Table 6.6.2
Table 6.6.3
Register Setting Up for Clock Divider ............................................................. 35
Input Signal Path Setting Up .......................................................................... 36
DATAPOLP & DATAPOLN Output ................................................................ 42
VSB Mode Data for Each VSB Mode ............................................................. 47
VSB Mode Signal Control .............................................................................. 47
Comb Filter Control through I²C Bus .............................................................. 49
Contents of I²C Bus Register33 for Equalizer ................................................ 55
Contents of I²C Bus Register33 for Filter Control .......................................... 55
Contents of I²C Bus Register33 for Phase Tracker ........................................ 59
Contents of I²C Bus Register33 for Gain Control ........................................... 59
Bypassed Sub-blocks by the Values of I²C Bus Register64 .......................... 60
Symbol-to-Byte Conversion ........................................................................... 64
I²C Register64 Flags controlling Transport Demultiplexer I/F ........................ 67
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