GDC21D003 Datasheet, PDF (46/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
This signal is changed to ‘0’ after detection of the
Field Sync signal. Then VSB Mode Detect is
activated. nSyncLock signal is used for
initialization of NTSC Rejection, Equalizer, Phase
Tracker, and Channel Decoder(FEC). If this signal
is ‘1’, it means the initialization state, if it is ‘0’, it
means the operation state. This signal is changed to
‘0’ after detection of the Field Sync signal and
FOE signal. If detected VSB mode from VSB
mode detect is different from existing one, NTSC
Rejection, Equalizer, Phase Tracker, and Channel
Decoder(FEC) are operated in new VSB mode. But
since Equalizer and Phase Tracker are consisted of
lots of feed back loops, these 2 blocks operated in
existing VSB mode can be invalid when they
suddenly should be operated on new VSB mode. In
this case, nSyncLock signal can initialize again
these blocks for normal operation, which may bring
the increase of system Lock up time. These 2 cases
have trade-off respectively that nSyncLock signal
can be initialized through nSyncLockrst(in I²C bus
register4) signal or not on the change of VSB mode.
If nSyncLockrst signal is ‘0’, it isn’t initialized on
every change of VSB mode, if it’s ‘1’, it is
initialized.
6.3.9 VSB Mode Detect
After Field Sync Recovery completed, VSB
mode of current transmitted signal should be
searched. There are 6 types of VSB mode
suggested till now, they are ATSC(terrestrial) 8
VSB, ATSC 16VSB, MMDS(cable) 2VSB, MMDS
4 VSB, MMDS 8VSB, and MMDS 16 VSB. But as
ATSC 16VSB and MMDS 16VSB are identical, in
fact there are 5 VSB modes. Field Sync in figure
6.3.13 has the information of current transmitted
VSB mode. 24-symbol VSB Mode signal is
detected in field Sync interval of input signal and
VSB Mode is generated. VSB mode data on each
mode is shown in Table 6.3.3. Among VSB mode
data, bold letter number is original VSB mode
signal, and italic is derivative signal. Mode signal
of MMDS 16 VSB and ATSC 16 VSB mode signal
can use “100” and “001”, but in this chip output is
always “100” regardless of input.
Table 6.3.3 VSB Mode Data for each VSB Mode
VSB Mode
MMDS 2 VSB
MMDS 4 VSB
MMDS 8 VSB
MMDS 16 VSB/ATSC 16VSB
ATSC 8 VSB
VSB Mode Data
“000011110000111100001111”
“000011110000111110010110”
“000011110000111110100101”
“000011110000111111000011”
(“000011110000111100111100”)
“000010100101111101011010”
VSB Mode Detect block can be variously
controlled through I²C bus. And internally detected
VSB mode can be read through I²C bus.
(VSBmodA[2:0] : in I²C bus register11) Table
6.3.4 shows the creation of VSB mode signal
through I²C bus.
NI2CEN
(pin number 39)
‘1’
‘0’
‘0’
Table 6.3.4 VSB Mode Signal Control
VSBmodW
(in I²C bus register4)
don’t care
‘1’
‘0’
VSBmod[2:0]
(in I²C bus register2)
don’t care
VSBmod[2:0]
don’t care
VSB Mode
ATSC 8VSB(“101”)
VSB mod[2:0]
Internally detected
VSB mode
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