GDC21D003 Datasheet, PDF (42/77 Pages) Hynix Semiconductor – VSB Receiver

6.3.7 Timing Recovery
In current DTV system, timing information is
extracted from inputted Data Segment Sync signal
and the clock used for digital processing and A/D.
Timing Recovery structure used in this chip is
similar to typical PLL structure. PLL generally
GDC21D003
consists of phase detector, loop filter, and
VCO(VCXO). In this chip, Timing Recovery is
consisted of internal Digital Phase Detector,
external analog device, Charge Pump, Loop Filter
and VCXO. Figure 6.3.10 is Timing Recovery
block diagram.
output of polarity correct
Correlator
PWM
Digital Phase Detector
CHGUP
Charge
CHGDN _Pump
Loop
Filter
VCXO ^CLOCK
Figure 6.3.10 Timing Recovery Block
On-chip Phase Detector extracts phase information
only in Data Segment Sync interval, and it is
activated after finding Data Segment Sync interval
inserted in transmitter. SEGSYNCLOCK(PIN46)
shows whether Data Segment Sync is found or not.
If this signal is ‘0’, Data Segment Sync isn’t found,
if this is ‘1’, it is found.
Phase detector uses filter whose coefficient is (-1,-
1,1,1) because it uses Data Segment Sync
pattern(1,0,0,1) to get phase information. Phase
information is converted again to PWM signal and
output from chip(NCHGUP/ NCHGDN).
While SEGSYNCLOCK signal is ‘0’,
NCHGUP/NCHGDN signal outputs are all ‘0’. In
this time, external Charge Pump is charged to free-
run voltage of VCXO.
When SEGSYNCLOCK signal is changed to ‘1’,
NCHGUP/NCHGDN signals are all changed to ‘1’,
and once per every Data Segment, charge of
external Charge Pump is charged up and down.
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