GDC21D003 Datasheet, PDF (3/77 Pages) Hynix Semiconductor – VSB Receiver

GDC21D003
TABLE OF CONTENTS
1. General Description................................................................................................................. 8
2. Features .................................................................................................................................... 8
3. Internal Block Diagram.......................................................................................................... 11
4. Pin Description....................................................................................................................... 11
4.1 Pin Configuration .............................................................................................................. 11
4.2 Pin Description.................................................................................................................. 14
4.3 Pin Assignment................................................................................................................. 16
5. I²C Bus I/F & Registers .......................................................................................................... 17
5.1 I²C Bus I/F Description...................................................................................................... 17
5.1.1 Write Operation ........................................................................................................... 17
5.1.2 Read Operation ........................................................................................................... 17
5.2 I²C Bus Register Configuration ......................................................................................... 18
5.3 I²C Bus Register Description ............................................................................................ 20
6. Functional Description .......................................................................................................... 29
6.1 ADC .................................................................................................................................. 29
6.1.1 Electrical Characteristics............................................................................................. 30
6.1.2 Timing Diagram ........................................................................................................... 32
6.1.3 Application Circuits...................................................................................................... 33
6.2 Clock Divider..................................................................................................................... 35
6.3 Synchronizer ..................................................................................................................... 36
6.3.1 Input Control................................................................................................................ 36
6.3.2 DC Reduction .............................................................................................................. 39
6.3.3 Auto Gain Control(AGC) ............................................................................................. 39
6.3.4 Polarity Correction....................................................................................................... 40
6.3.5 Data Segment Sync Recovery .................................................................................... 41
6.3.6 Polarity Decision.......................................................................................................... 42
6.3.7 Timing Recovery ......................................................................................................... 43
6.3.8 Field Sync Recovery ................................................................................................... 46
6.3.9 VSB Mode Detect........................................................................................................ 47
6.3.10 NTSC Rejection......................................................................................................... 48
6.4 Equalizer ........................................................................................................................... 50
6.4.1 Block Diagram ............................................................................................................. 50
6.4.2 Training/Data Mode Equalization ................................................................................ 51
6.4.3 Error Estimation........................................................................................................... 52
6.4.4 Adaptive Filter ............................................................................................................. 53
6.4.5 Equalizer Clock Scheme ............................................................................................. 53
6.4.6 I²C Bus I/F ................................................................................................................... 54
6.4.7 Coefficient Reading/Writing......................................................................................... 56
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